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LMH6555 Low Distortion 1.2 GHz Differential Driver
December 3, 2007
LMH6555 Low Distortion 1.2 GHz Differential Driver
General Description
The LMH6555 is an ultra high speed differential line driver with 53 dB SFDR at 750 MHz. The LMH6555 features a fixed gain of 13.7 dB. An input to the device allows the output common mode voltage to be set independent of the input common mode voltage in order to simplify the interface to high speed differential input ADCs. A unique architecture allows the device to operate as a fully differential driver or as a singleended to differential converter. The outstanding linearity and drive capability (100 differential load) of this device are a perfect match for driving high speed analog-to-digital converters. When combined with the ADC081000/ ADC081500 (single or dual ADC), the LMH6555 forms an excellent 8-bit data acquisition system with analog bandwidths exceeding 750 MHz. The LMH6555 is offered in a space saving 16-pin LLP package.
Features
Typical values unless otherwise specified. -3 dB bandwidth (VOUT = 0.80 VPP) 0.5 dB gain flatness (VOUT = 0.80 VPP) Slew rate 2nd/3rd Harmonics (750 MHz) Fixed gain Supply current Single supply operation Adjustable common-mode output voltage 1.2 GHz 330 MHz 1300 V/s -53/-54 dBc 13.7 dB 120 mA 3.3V 10%
Applications
Differential ADC driver National Semiconductor ADC081500/ ADC081000
(single or dual) driver Single ended to differential converter Intermediate frequency (IF) amplifier Communication receivers Oscilloscope front end
Typical Application
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Single Ended to Differential Conversion
(c) 2007 National Semiconductor Corporation
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 5) Human Body Model Machine Model VS Output Short Circuit Duration (one pin to ground) Common Mode Input Voltage 2000V 200V 4.2V Infinite -0.4V to 3V (Note 2)
Maximum Junction Temperature Storage Temperature Range Soldering Information Infrared or Convection (20 sec.) Wave Soldering (10 sec.)
+150C -65C to +150C 235C 260C
Operating Ratings
Temperature Range (Note 4) Supply Voltage Range
(Note 1) -40C to +85C +3.3V 10% 65C/W
Package Thermal Resistance (JA)(Note 4) 16-Pin LLP
3.3V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TA= 25C, VCM_REF = 1.2V, both inputs tied to 0.3V through 50 (RS1 & RS2) each (Note 11), VS = 3.3V, RL = 100 differential, VOUT = 0.8 VPP. See the Definition of Terms and Specification section for definition of terms used throughout the datasheet. Boldface limits apply at the temperature extremes. Symbol AC/DC Performance SSBW LSBW Peak GF_0.1 dB GF_0.5 dB Ph_Delta Lin_Ph GD P_1 dB TRS/TRL OS SR ts AV_DIFF Phase Delta Linear Phase Deviation Group Delay 1 dB Compression Rise/ Fall Time Overshoot Slew Rate Settling Time Insertion Gain (|S21|) Peaking Gain Flatness -3 dB Bandwidth VOUT = 0.25 VPP VOUT = 0.8 VPP VOUT = 0.8 VPP 0.1 dB 0.5 dB Output Differential Phase Difference f 1.2 GHz Each Output f 2 GHz Each Output f 2 GHz 1 GHz VOUT = 0.2 VPP Each Output VOUT = 0.2 VPP Each Output 0.8V Step, 10% to 90%,(Note 6) 1% 13.2 13.1 1 320 14 1300 2.2 13.7 14.0 14.1 VPP pS % V/s ns dB 0.75 ns < 30 deg 1200 1200 1.4 180 330 < 0.8 MHz dB MHz deg Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units
TC AV_DIFF AV_DIFF1 AV_DIFF2
Temperature Coefficient of Insertion Gain Insertion Gain Variation with VCM_REF Insertion Gain Variation with VI_CM 2nd Harmonic Distortion VCM_REF Input Varied from 0.95V to 1.45, VOUT = 0.8 VPP -0.3 VI_CM 2.0V
-0.9 -0.04 0.03 0.50 0.58 0.48 0.55
mdB/C dB dB
Distortion And Noise Response HD2_L HD2_M HD2_H HD3_L HD3_M HD3_H 3rd Harmonic Distortion 250 MHz (Note 12) 500 MHz (Note 12) 750 MHz (Note 12) 250 MHz (Note 12) 500 MHz (Note 12) 750 MHz (Note 12) -60 -62 -53 -67 -61 -54 dBc dBc
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Symbol OIP3
Parameter
Conditions
Min (Note 8)
Typ (Note 7) 27.5
Max (Note 8)
Units dBm
Output 3rd Order Intermodulation f = 1 GHz Intercept POUT (Each Tone) 8.5 dBm (Notes 12, 13) 3rd Order Intermodulation Distortion Output Referred Voltage Noise Noise Figure f = 1 GHz POUT (Each Tone) = -6 dBm (Notes 12, 13)
OIM3
-67
dBc
eno NF
1 MHz
Relative to a Differential Input
19 15.0
nV/ dB
10 MHz
Input Characteristics RIN RIN_DIFF CIN CMRR CM Input Resistance Differential Input Resistance Input Capacitance Common Mode Rejection Ratio Each Input to Ground Differential Each Input to GND -0.3 CMVR 2.0V 40 36 45 66 50 78 0.3 68 55 100 pF dB
Output Characteristics VOOS TCVOOS RO BAL_Error_DC Output Offset Voltage Output Offset Voltage Average Drift Output Resistance Output Gain Balance Error Differential Mode (Note 9) RT1 and RT2 43 15 100 50 -57 53 -38 dB 50 55 mV V/C
BAL_Error_AC
-48
BAL_Error_AC_ Output Phase Balance Error Phase |VO_CM/VI_CM| Output Common Mode Gain VCM_REF Characteristics VOS_CM TC_VOS_CM IB_CM RIN_CM Gain_VCM_REF Power Supply IS PSRR PSRR_CM Supply Current Differential Power Supply Rejection Ratio Common Mode PSRR Output CM Offset Voltage CM Offset Voltage Temp Coefficient VCM_REF Bias Current VCM_REF Input Resistance VCM_REF Input Gain to Output
f = 750 MHz, VOUT+ - VOUT- Phase DC
0.6 -26 -22 -21 60 85
deg
dB
VOS_CM = VO_CM - VCM_REF
-4 -0.2
mV mV/C
0.95V VCM_REF 1.45V (Note 10) 3.5 VO_CM/VCM_REF RS1 & RS2 Open (Note 3) DC, VS = 0.3V, VOUT/VS DC, VS = 0.3V, VO_CM/VS -27 -25 -29 -27 0.97
-25 5.8 0.99 120 -44 -39
390 415 1.00 150 156
A k V/V
mA dB dB
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 3: Total supply current is affected by the input voltages connected through RS1 and RS2. Supply current tested with input removed. Note 4: The maximum power dissipation is a function of TJ(MAX), JA and TA. The maximum allowable power dissipation at any ambient temperature is PD= (TJ(MAX) -- TA)/ JA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow. Package should be soldered unto a 6.8 mm2 copper area as shown in the "recommended land pattern" shown in the package drawing. Note 5: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 6: Slew Rate is the average of the rising and falling edges. Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 8: Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 9: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Note 10: Positive current is current flowing into the device. Note 11: Quiescent device common mode input voltage is 0.3V. Note 12: Distortion data taken under single ended input condition. Note 13: 0 dBm = 894 mVPP across 100 differential load
Ordering Information
Package 16-Pin LLP Part Number LMH6555SQ LMH6555SQE LMH6555SQX L6555SQ Package Marking Transport Media 1k Units Tape and Reel 250 Units Tape and Reel 4.5k Units Tape and Reel SQA16A NSC Drawing
Connection Diagram
16-Pin LLP
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Definition of Terms and Specifications (Alphabetical Order)
Unless otherwise specified, VCM_REF = 1.2V 1. 2. 3. 4. AV_CM (dB) AV_DIFF (dB) AV_DIFF (dB) BAL_ERR_DC & BAL_ERR_AC CM CMRR (dB) CMVR (V) Gain_VCM_REF (V/V) PSRR (dB) PSRR_CM (dB) RIN () RIN_DIFF () RL () RO () RS1, RS2 () RT1, RT2 () VCM_REF (V) VCM_REF (V) VI_CM (V) VI_CM (V) VIN+, VIN- (V) VIN (V) VO_CM (V) VO_CM (V) Common Mode Common Mode rejection defined as: AV_DIFF (dB) - AV_CM (dB) Range of input common mode voltage (VI_CM) Variation in output common mode voltage (VO_CM) with respect to change in VCM_REF input (VCM_REF) with maximum differential output Differential output change (VOUT) with respect to the power supply voltage change (VS) with nominal differential output Output common mode voltage change (VO_CM) with respect to the change in the power supply voltage (VS) 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. Single ended input impedance to ground Differential input impedance Differential output load Device output impedance equivalent to RT1 & RT2 Source impedance to VIN+ and VIN- respectively Output impedance looking into each output Device input pin which controls output common mode Change in the VCM_REF input DC average of the inputs (VIN+, VIN-) or the common mode signal at those same input pins Variation in input common mode voltage (VI_CM) Device input pin voltages Terminated (50 for single ended and 100 for differential) generator voltage Output common mode voltage (DC average of VOUT+ and VOUT-) Variation in output common mode voltage (VO_CM) Balance Error. Measure of the output swing balance of VOUT+ and VOUT-, as reflected on the output common mode voltage (VO_CM), relative to the differential output swing (VOUT). Calculated as output common mode voltage change (VO_CM) divided into the output differential voltage change (VOUT which is nominally around 800 mVPP) 26. Change in the differential output voltage (VOUT ) with respect to the change in input common mode voltage (VI_CM) Insertion gain from a single ended 50 (or 100 differential) source to the differential output (VOUT) Variation in insertion gain (AV_DIFF)
5. 6. 7. 8. 9. 10.
27. 28. 29. 30. 31. 32. 33.
VOOS (V) VOS_CM (V) VOUT (V) VOUT (V) VOUT+, VOUT- (V) VS (V) VS (V)
DC Offset Voltage. Differential output voltage measured with both inputs grounded through 50 Difference between the output common mode voltage (VO_CM) and the voltage on the VCM_REF input, for the allowable VCM_REF range Differential Output Voltage (VOUT+ - VOUT-) (Corrected for DC offset (VOOS)) Change in the differential output voltage (Corrected for DC offset (VOOS)) Device output pin voltages Supply Voltage (V+ - V-) Change in VCC supply voltage
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Typical Performance Characteristics
Unless otherwise specified, RS1 = RS2 = 50, VS = 3.3V, RL = 100 differential, VOUT = 0.8 VPP. See the Definition of Terms and Conditions section for definition of terms used throughout the datasheet. Frequency Response 0.5 dB Gain Flatness
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Linear Phase Deviation & Group Delay
Bal_Error vs. Frequency
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-1 dB Compression vs. Frequency
Step Response (VOUT+)
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Step Response Settling Time
Harmonic Distortion vs. Frequency
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3rd Order Intermodulation Distortion
AV_DIFF & RIN_DIFF vs. VI_CM
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Insertion Gain Distribution
Insertion Gain Variation vs. Input Amplitude
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PSRR & PSRR_CM vs. Frequency
CMRR vs. VI_CM
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CMRR vs. Frequency
Noise Density & Noise Figure
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S_Parameters vs. Frequency
Differential Output Offset Variation for 3 Representative Units
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Common Mode Offset Voltage Variation vs. VCM_REF
Supply Current vs. Temperature
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Application Information
See the Definition of Terms and Conditions section for definition of terms used. GENERAL The LMH6555 consists of three individual amplifiers: The VOUT+ driver, VOUT- driver, and the common mode amplifier. Being a differential amplifier, the LMH6555 will not respond to the common mode input (as long as it is within its input common mode range) and instead the output common mode
is forced by the built-in common mode amplifier with VCM_REF as its input. As shown, in Figure 1 below, the VCMO output of most differential high speed ADC's is tied to the VCM_REF input of the LMH6555 for direct output common mode control. In some cases, the output drive capability of the ADC VCMO output may need an external buffer, as shown, to increase its current capability in order to drive the VCM_REF pin. The LMH6555 Electrical Characteristics table shows the gain (Gain_VCM_REF) and the offset (VOS_CM) from the VCM_REF to the device output common mode.
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FIGURE 1. Single Ended to Differential Conversion The single ended input and output impedances of the LMH6555 I/O pins are close to 50 as specified in the Electrical Characteristics table (RIN and RO). With differential input drive, the differential input impedance (RIN_DIFF) is close to 78. The device nominal input common mode voltage (VI_CM) is close to 0.3V when RS1 and RS2 of Figure 1 are open. Thus, the input source will experience a DC current with 0V input. Because of this, the differential output offset voltage is influenced by the matching between RS1 and RS2. So, in a single ended input condition, if the signal source is AC coupled to one input, the undriven input needs to also be AC coupled in order to cancel the output offset voltage (VOOS). In applications where low output offset is required, it is possible to inject some current to the appropriate input (VIN+ or VIN-) as an effective method of trimming the output offset voltage of the LMH6555. This is explained later in this document. The nominal value of RS1 and RS2 will also affect the insertion gain (AV_DIFF). The LMH6555 can also be used with the input AC coupled through equal valued DC blocking capacitors (C) in series with VIN+ and VIN-. In this case, the coupling capacitors need to be large enough to not block the low frequency content. The lower cutoff frequency will be 1/(REQC)Hz with REQ= RS1+ RS2 + RIN_DIFF where RIN_DIFF 78. The single ended output impedance of the LMH6555 is 50. The LMH6555 Electrical Characteristics shows the device performance with 100 differential output load, as would be the case if a device such as the ADC081000/ ADC081500 (single/ dual ADC) were being driven.
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CIRCUIT ANALYSIS Figure 2 shows the block diagram of the LMH6555.
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RG1 = RG2 = RG = 39 RE1 = RE2 = RE = 25 RF1 = RF2 = RF = 430 ICQ1 = ICQ2 = 12.6 mA
FIGURE 2. Block Diagram The differential input stage consists of cross-coupled common base bipolar NPN stages, Q1 and Q2. These stages give the device its differential input characteristic. The internal loop gain from Vx and Vy internal nodes (Q1 and Q2 emitters) to the output is large, such that these nodes act as a virtual ground. The cross-coupling will ensure that these nodes are at the same voltage as long as the amplifier is operating within its normal range. Output common mode voltage is enforced through the action of "ACM" which servos the output common mode to the "VCM_REF" input voltage. The discussion that follows, provides the formulas needed to analyze single ended and differential input applications. For a more detailed explanation including derivations, please see the Appendix at the end of the datasheet.
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SINGLE-ENDED INPUT The following is the procedure for determining the device operating conditions for single ended input applications. This example will use the schematic shown in Figure 3.
VIN_DIFF = IIN_DIFF * RIN_DIFF
For Figure 3
VIN_DIFF = 1.685 mAPP * 78 = 131.4 mVPP
5. Calculate the undriven input's swing, based on VIN_DIFF determined in step 4 and VIN+ calculated in step 1:
VIN- = VIN+ - VIN_DIFF
For Figure 3
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VIN- = 150 mVPP - 131.4 mVPP = 18.6 mVPP
6. Determine the DC average of the two inputs (VI_CM) by using the following expression:
FIGURE 3. Single-Ended Input Drive 1. Determine the driven input's (VIN+ or VIN-) swing knowing that each input common mode impedance to ground (RIN) is 50:
VIN+ (or VIN-) = VIN * RIN/(RIN + RS)
For Figure 3
VI_CM = 12.6 mA * RE * RS / (RS + RG + RE) where RE = 25 & RG = 39 (both internal to the LMH6555)
For Figure 3
VIN+ = 0.3 VPP * 50/(50+50) = 0.15 VPP
2. Calculate VOUT knowing the Insertion Gain (AV_DIFF):
RS = 50 VI_CM = 15.75 / (RS + 64) VI_CM = 15.75/ (50+64) = 138.2 mV
The values determined with the procedure outlined here are shown in Figure 4.
VOUT = (VIN/2) * AV_DIFF AV_DIFF = 2 * RF/ (2RS + RIN_DIFF) where RF = 430 & RIN_DIFF = 78
For Figure 3
RS = 50 AV_DIFF = 4.83 V/V VOUT = (0.3 VPP/2) * 4.83 V/V= 724.5 mVPP
3. Determine the peak-to-peak differential current (IIN_DIFF) through the device's differential input impedance (RIN_DIFF) which would result in the VOUT calculated in step 2:
IIN_DIFF = VOUT/ RF
For Figure 3
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IIN_DIFF = 724.5 mVPP/ 430 = 1.685 mAPP
4. Determine the swing across the input terminals (VIN_DIFF) which would give rise to the IIN_DIFF calculated in step 3 above.
FIGURE 4. Input Voltage for Figure 3 Schematic
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DIFFERENTIAL INPUT The following is the procedure for determining the device operating conditions for differential input applications using the Figure 5 schematic as an example.
The values determined with the procedure outlined here are shown in Figure 6.
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Assuming transformer secondary, VIN, of 300 mVPP
FIGURE 5. Differential Input Drive 1. Calculate the swing across the input terminals (VIN_DIFF) by considering the voltage division from the differential source (VIN) to the LMH6555 input terminals with differential input impedance RIN_DIFF:
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FIGURE 6. Input Voltage for Figure 5 Schematic SOURCE IMPEDANCE(S) AND THEIR EFFECT ON GAIN AND OFFSET The source impedances RS1 and RS2, as shown in Figure 3 or Figure 5, affect gain and output offset. The datasheet tables and typical performance graphs are generated with equal valued source impedances RS1 and RS2, unless otherwise specified. Any mismatch between the values of these two impedances would alter the gain and offset voltage. OUTPUT OFFSET CONTROL AND ADJUSTMENT There are applications which require that the LMH6555 differential output voltage be set by the user. An example of such an application is a unipolar signal which is converted to a differential output by the LMH6555. In order to utilize the full scale range of the ADC input, it is beneficial to shift the LMH6555 outputs to the limits of the ADC analog input range under minimal signal condition. That is, one LMH6555 output is shifted close to the negative limit of the ADC analog input and the other close to the positive limit of the ADC analog input. Then, under maximum signal condition, with proper gain, the full scale range of the ADC input can be traversed and the ADC input dynamic range is properly utilized. If this forced offset were not imposed, the ADC output codes would be reduced to half of what the ADC is capable of producing, resulting in a significant reduction in ENOB. The choice of the direction of this shift is determined by the polarity of the expected signal. Another scenario where it may be necessary to shift the LMH6555 output offset voltage is in applications where it is necessary to improve the specified Output Offset Voltage (differential mode), "VOOS". Some ADC's, including the ADC081000/ ADC081500 (and their dual counterparts), have internal registers to correct for the driver's (LMH6555) VOOS. If the LMH6555 VOOS rating exceeds the maximum value allowed into this register, then shifting the output is required for maximum ADC performance. It is possible to affect output offset voltage by manipulating the value of one input resistance relative to the other (e.g. RS1 relative to RS2 or vice versa). However, this will also alter the gain. Assuming that the source is applied to the VIN+ side through RS1, Figure 7(A) shows the effect of varying RS1 on the overall gain and output offset voltage. Figure 7(B) shows the same effects but this time for when the undriven side impedance, RS2, is varied.
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VIN_DIFF = VIN * RIN_DIFF/ (2RS + RIN_DIFF)
For Figure 5
VIN_DIFF = 300 mVPP * 78 / (100 + 78) = 131.5 mVPP
2. Calculate each input pin swing to be 1/2 the swing determined in step 1:
VIN+ = VIN- = VIN_DIFF/ 2
For Figure 5
VIN+ = VIN- = 131.5 mVPP/ 2 = 65.7 mVPP
3. Determine the DC average of the two inputs (VI_CM) by using the following expression:
VI_CM = 12.6 mA * RE * RS / (RS + RG + RE) where RE = 25 & RG = 39 (both internal to the LMH6555)
For Figure 5
RS = 50 VI_CM = 15.75 / (RS+ 64) VI_CM = 15.75/ (50+64) = 138.2 mV
4. Calculate VOUT knowing the Insertion Gain (AV_DIFF):
VOUT = (VIN * / 2) * AV_DIFF AV_DIFF = 2 * RF/ (2RS + RIN_DIFF) where RF= 430 & RIN_DIFF = 78
For Figure 5
RS = 50 AV_DIFF = 4.83 V/V VOUT = (0.3 VPP/2) * 4.83 V/V= 724.5 mVPP
LMH6555
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FIGURE 8. Gain & Output Offset Voltage vs. Source Impedance Shift for Differential Input Drive It is possible to manipulate output offset with little or no effect on source resistance balance, gain, and, cable termination.
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FIGURE 7. Gain & Output Offset Voltage vs. Source Impedance Shift for Single Ended Input Drive As can be seen in Figure 7, the source impedance of the input side being driven has a bigger effect on gain than the undriven source impedance. RS1 and RS2 affect the output offset in opposite directions. Manipulating the value of RS2 for offset control has another advantage over doing the same to RS1 and that is the signal input termination is not affected by it. This is especially important in applications where the signal is applied to the LMH6555 through a transmission line which needs to be terminated in its characteristic impedance for minimum reflection. For reference, Figure 8 shows the effect of source impedance misbalance on overall gain and output offset voltage with differential input drive.
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(a)
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(b) FIGURE 9. Differential Output Shift Circuits RX, shown in Figure 9(a) and Figure 9(b), injects current into the input to achieve the required output shift. For a positive shift, positive current would need to be injected into the VIN+ terminal (Figure 9(a)) and for a negative shift, to the VIN- terminal (Figure 9(b)). Figure 10 shows the effect of RX on the output with VX = 3.3V or 5V, and RS1 = RS2 = 50.
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From the gain expression in Equation 4 (see Appendix) (but with opposite polarity because VTH is applied to VIN- instead):
(1) The expression derived for VOUT in Equation 1 can be set equal to zero to solve for RX resulting in RX = 4.95 k. If the differential output offset voltage, VOOS, is also known, VOUT could be set to a value equal to -VOOS. For example, if the VOOS for the particular LMH6555 is +30 mV, then the following nulls the differential output:
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FIGURE 10. LMH6555 Differential Output Shift Due to RX in Figure 9 To shift the LMH6555 differential output negative by about 100 mV, referring to the plot in Figure 10, RX would be chosen to be around 3.9 k in the schematic of Figure 9(b) (using VX = VS = 3.3V). In applications where VIN has a built-in non-zero offset voltage, or when RS1 and RS2 are not 50, the Figure 10 plot cannot be used to estimate the required value for RX. Consider the case of a more general offset correction application, shown in Figure 11(a), where RS1 = RS2 = 75 and VIN has a built-in offset of -50 mV. It is necessary to shift the differential output offset voltage of the LMH6555 to 0 mV. Figure 11(b) is the Thevenin equivalent of the circuit in Figure 11(a) assuming RX >> RS2.
(2) RX >> RS2 confirming the assumption made in the derivation. Note that Equation 2, which is derived based on the configuration in Figure 9(b), will yield a real solution for RX if and only if:
(3) where VIN_OFFSET is the source offset shown as -50 mV in Figure 11(a). If Equation 3 were not satisfied, then Figure 9(a) offset correction, where RX is tied to the VIN+ side, should be employed instead. Alternatively, replace the VX and RX combination with a discrete current source or current sink. Because of a current source's high output impedance, there will be less gain imbalance. However, a current source might have a relatively large output capacitance which could degrade high frequency performance. INTERFACE DESIGN EXAMPLE As shown in Figure 12 below, the LMH6555 can be used to interface an open collector output device (U1) to a high speed ADC. In this application, the LMH6555 performs the task of amplifying and driving the 100 differential input impedance of the ADC.
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(a)
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(b) FIGURE 11. Offset Correction Example (RS = 75)
VCM_REF buffer not shown
FIGURE 12. Differential Amplification and ADC Drive
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For applications similar to the one shown in Figure 12, the following conditions should be maintained: 1. The LMH6555 differential output voltage has to comply with the ADC full scale voltage (800 mVPP in this case). 2. The LMH6555 input Common Mode Voltage Range is observed. "CMVR", as specified in the Electrical Characteristics table, is to be between -0.3V and 2.0V for the specified CMRR. 3. U1 collector voltage swing must to be observed so that the U1 output transistors do not saturate. The expected operating range of these output transistors is defined by the specifications and operating conditions of U1. Consider a numerical example (RL refers to RL1 & RL2, RS refers to RS1 & RS2). Assume: VCC = 10V, U1 peak-to-peak collector current (IPP) = 15 mAPP with 10 mA quiescent (IcQ), and minimum operational U1 collector voltage = 6V. Here are the series of steps to take in order to carry out this design: a. Select the RL value which allows compliance with the U1 collector voltage (6V in this case) with 1V extra as margin because of LMH6555 loading. RL = [10 - (6+1)] V / (10+ 7.5) mA = 171 Choose 169, 1% resistors for RL b. Find the value of RS to get the proper swing at the output (800 mVPP). To do so, convert the input stage into its Norton equivalent as shown in Figure 13.
IN (differential) * RF = 800 mVPP
RS = (RL* IPP * RF/ 0.8) - RG - RL where RF = 430,
RG = 39 (RF and RG are internal LMH6555 resistances). So, in this case: RS = (169 * 15 mAPP * 430/ 0.8) - 39 - 169 = 1154 Choose 1.15 k, 1% resistors for RS. c. With RL and RS defined, ensure that the U1 collector voltage(s) minimum is not violated due to the loading effect of the LMH6555 through RS. Also, it is important to ensure that the LMH6555's CMVR is also not violated. The "Vx" node voltage within the LMH6555 (see Figure 13) would need to be calculated. Use the Common Mode component of the Norton equivalent source from above, and write the KCL at the Vx node as follows: Vx / RE + Vx / RN = 12.6 mA + IN (common mode); with RE = 25. Vx / RE + Vx / RN = 12.6 mA + (VCC - IcQ RL )/ (RL + RS + RG)
Vx = 0.4595V
With Vx calculated, both the input voltage range (high and low) and the low end of the U1 collector voltage (VC) can be derived to be within the acceptable range. If necessary, steps "a" through "c" would have to be repeated to readjust these values. VC = VX RL / RN + IN (RS + RG) IN_High = 7.05 mA, IN_Low = 5.19 mA (based on the values derived)
VC_High = 0.4595 * 169 / 1358 + 7.05 mA (1150 + 39)
= 8.44V
VC_Low = 0.4595 * 169 / 1358 + 5.19 mA (1150 + 39)
= 6.22V VIN = VX (RN - RG) / RN + IN RG
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VIN_High = 0.4595 * (1358- 39) / 1358 + 7.05 mA * 39
= 0.721V
FIGURE 13. Norton Equivalent of the Input Circuitry Tied to Q1 within the LMH6555 in Figure 12 IN = IN (common mode) + IN (differential) IN (common mode) = (VCC - IcQ * RL) / (RL + RS + RG) IN (differential) = IPP * RL / (RL + RS + RG) The entirety of the Norton source differential component will flow through the feedback resistors within the LMH6555 and generate an output. Therefore:
VIN_Low = 0.4595 * (1358- 39) / 1358 + 5.19 mA * 39
= 0.649V Figure 14 shows the complete solution using the values derived above, with the node voltages marked on the schematic for reference.
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VC_High = 10 - 80.6 (10 + 15 / 2 - 1.88 /2) mA = 8.67V VC_Low = 10 - 80.6 (10 - 15 / 2 + 1.88 /2) mA = 9.72V
VIN = VX RG. IN (differential) /2
VIN_High = 0.3150 + 39 * 1.88 mA /2 = 0.3517V VIN_Low = 0.3150 - 39 * 1.88 mA /2 = 0.2783V
Figure 16 shows the AC coupled implementation of the Figure 15 schematic along with the node voltages marked to demonstrate the reduced VI_CM of the LMH6555 and the increase in the U1 collector voltage minimum.
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FIGURE 14. Implementation #1 of Figure 12 Design Example It is important to note that the matching of the resistors on either input side of the LMH6555 (RS1 to RS2 and RL1 to RL2) is very important for output offset voltage and gain balance. This is particularly true with values of RS higher than the nominal 50. Therefore, in this example, 1% or better resistor values are specified. If the U1 collector voltage turns out to be too low due to the loading of the LMH6555, lower RL. Lower values of RL result in lower RS which in turn increases the LMH6555's VI_CM because of increased pull up action towards VCC. The upper limit on VI_CM is 2V. Figure 15 shows the 2nd implementation of this same application with lowered values of RL and RS. Notice that the lower end of U1's collector voltage and the upper end of LMH6555's VI_CM have both increased compared to the 1st implementation.
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FIGURE 16. AC Coupled Version of Figure 15 Note that the lower cut-off frequency is: f_cut-off = 1 / (ReqCS) where Req = RS1+ RS2 + RIN_DIFF where RIN_DIFF 78 So, for the component values shown (CS = 0.01 F and RS1 = RS2 = 523): f_cut-off = 28.2 kHz DATA ACQUISITION APPLICATIONS Figure 17 shows the LMH6555 used as the differential driver to the National Semiconductor ADC081500 running at 1.5G samples/second.
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FIGURE 15. Implementation #2 of Figure 12 Design Example An alternative would be to AC couple the LMH6555 inputs. With this approach, the design steps would be very similar to the ones outlined except that there would be no common mode interaction between the LMH6555 and U1 and this results in fewer design constraints: Vx / RE = 12.6 mA Vx = 0.3150V For the component values shown in Figure 15 use: VC_High = VCC - RL (IcQ + IPP / 2 - IN (differential) /2) VC_Low = VCC - RL (IcQ - IPP / 2 + IN (differential) /2) IN (differential) = IPP * RL / (RL + RS + RG) = 1.88 mA (based on the values used.)
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FIGURE 17. Schematic of the LMH6555 Interfaced to the ADC081500
LMH6555
In the schematic of Figure 17, the LMH6555 converts a single ended input into a differential output for direct interface to the ADC's 100 differential input. An alternative approach to using the LMH6555 for this purpose, would have been to use a balun transformer, as shown in Figure 18.
shows CO placed across the LMH6555 output terminals to reduce the frequency response gain peaking and thereby to increase the 0.5 dB gain flatness frequency.
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FIGURE 18. Single Ended to Differential Conversion (AC only) with a Balun Transformer In the circuit of Figure 18, the ADC will see a 100 differential driver which will swing the required 800 mVPP when VIN is 1.6 VPP. The source (VIN) will see an overall impedance of 200 for the frequency range that the transformer is specified to operate. Note that with this scheme, the signal to the ADC must be AC coupled, because of the transformer's minimum operating frequency which would prevent DC coupling. For the transformer specified, the lower operating frequency is around 4.5 MHz and the input high pass filter's -3 dB bandwidth is around 340 kHz for the values shown (or (1/REQC) Hz where REQ = 200). Table 1 compares the LMH6555 solution (Figure 17) vs. that of the balun transformer coupling (Figure 18) for various categories. TABLE 1. ADC Input Coupling Schemes Compared Preferred Solution Category Lower Power Consumption Lower Distortion Wider Dynamic Range DC Coupling & Broadband Applications Highest Gain & Phase Balance Input/ Output Broadband Impedance Matching (Highest Return Loss) Additional Gain ADC Input Protection against Overdrive Highest SNR Ability to Control Gain Flatness LMH6555 Balun Transformer
FIGURE 19. Increasing 0.5 dB Gain Flatness using External Output Capacitance, CO Figures 20, 21 and Figure 22 show the FFT analysis results with the setup shown in Figure 17.

(see below)
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FIGURE 20. LMH6555 FFT Result When Used as the Differential Driver to ADC081500
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GAIN FLATNESS In applications where the full 1.2 GHz bandwidth of the LMH6555 is not necessary, it is possible to improve the gain flatness frequency at the expense of bandwidth. Figure 19
FIGURE 21. LMH6555 FFT Result When Used as the Differential Driver to ADC081500 (Lower Fs/2 Region Magnified)
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drive an ADC is determined by the application and the desired sampling process (Nyquist operation, sub-sampling or oversampling). See application note (AN-236) for more details on the sampling processes and application note (AN-1393) for details on "Using High Speed Differential Amplifiers to Drive ADCs". For more information regarding a particular ADC, refer to the particular ADC datasheet for details. TABLE 2. Differential Input ADC's Compatible with the LMH6555 Driver ADC Part Number Resolution (bits) ADC08D500 ADC081000
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Single/ Dual S S D D S D D S S
Speed (MSPS) 500 1000 1000 1000 1500 1500 1500 3000 3000
8 8 8 8 8 8 8 8 8
ADC08D1000 ADC08D1020 ADC081500 ADC08D1500 ADC08D1520 ADC083000 ADC08B3000
FIGURE 22. LMH6555 FFT Result When Used as the Differential Driver to ADC081500 (Upper Fs/2 Region Magnified) Figures 20, 21, and Figure 22 information summary: * Fundamental Test Frequency * LMH6555 Output * Sampling Rate: * 2nd Harmonic * 3rd Harmonic * 4th Harmonic * 5th Harmonic * 6th Harmonic * THD * SNR * Spurious Free Dynamic Range (SFDR): * SINAD * ENOB 744 MHz 0.8 VPP 1.5G samples/ second -59 dBc @ 12 MHz or |1.5 GHz*1- 744 MHz*2| -57 dBc @ 732 MHz or |1.5 GHz*1- 744 MHz *3| -71 dBc @ 24 MHz or |1.5 GHz*2 - 744 MHz *4| -68 dBc @ 720 MHz or |1.5 GHz*2- 744 MHz*5| -68 dBc @ 36 MHz or |1.5 GHz*3- 744 MHz*6| -51.8 dBc 43.4 dB 57 dB 42.8 dB 6.8 bits
EXPOSED PAD LLP PACKAGE The LMH6555 is in a thermally enhanced package. The exposed pad (device bottom) is connected to the GND pins. It is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. The thermal dissipation of the device is largely dependent on the connection of this pad. The exposed pad should be attached to as much copper on the circuit board as possible, preferably external copper. However, it is very important to maintain good high speed layout practices when designing a system board. Here is a link to more information on the National 16-pin LLP package: http://www.national.com/packaging/folders/sqa16a.html EVALUATION BOARD National Semiconductor suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing and characterization. Device LMH6555 Package 16-Pin LLP Evaluation Board Ordering ID LMH6555EVAL
The LMH6555 is capable of driving a variety of National Semiconductor Analog to Digital Converters. This is shown in Table 2, which offers a complete list of possible signal path ADC+ Amplifier combinations. The use of the LMH6555 to
The evaluation board can be ordered when a device sample request is placed with National Semiconductor.
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LMH6555
Appendix
Here is a more detailed analysis of the LMH6555, including the derivation of the expressions used throughout the Application Information. INPUT STAGE Because of the input stage cross-coupling, if the instantaneous values of the input node voltages (VIN+ and VIN-) and current values are required, use the circuit of Figure 23 as the equivalent input stage for each input (VIN+ and VIN-).
The first task would be to derive the internal transistor emitter voltages based on the schematic of Figure 23 (assuming that there is no interaction between the stages.) Here is the derivation of VX and Vy:
VX varies with VIN+ (0.213V with negative VIN swing and 0.279V with positive.) The values derived above assume that the two halves of the input circuit do not interact with each other. They do through the common mode amplifier and the input stage cross-coupling. Vx and Vy are equal to the average of Vy with either end of the swing of VX. This is calculated below along with the derivation of VIN+ and VIN- based on this new average emitter voltage (the average of VX and Vy.)
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FIGURE 23. Equivalent Input Stage Using this simplified circuit, one can assume a constant collector current, to simplify the analysis. This is a valid approximation as the large open loop gain of the device will keep the two collector currents relatively constant. First derive Q1 and Q2 emitter voltages. From there, derive the voltages at VIN+ and VIN-. With the component values shown, it is possible to analyze the input circuits of Figure 23 in order to determine Q1 and Q2 emitter voltages. This will result in a first order estimate of Q1 and Q2 emitter voltages. Since Q1 and Q2 emitters are cross-coupled, the voltages derived would have to be equal. With the action of the common mode amplifier, "ACM", shown in Figure 2, these two emitters will be equalized. So, one other iteration can be performed whereby both emitters are set to be equal to the average of the 1st derived emitter voltages. Using this new emitter voltage, one could recalculate VIN+ and VIN- voltages. The values derived in this fashion will be within 10% of the measured values. Single Ended Input Analysis Here is an actual example to further clarify the procedure. Consider the case where the LMH6555 is used as a single ended to differential converter shown in Figure 24.
With 0.3 VPP VIN, VIN+ experiences 150 mVPP (213 mV - 63.2 mV) of swing and VIN- will swing by about 18.6 mVPP in the process (147 mV - 129 mV). The input voltages are shown in Figure 25.
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FIGURE 25. Input Voltages for Figure 24 Schematic
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FIGURE 24. Single Ended Input Drive
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LMH6555
Using the calculated swing on VIN+ with known VIN, one can estimate the input impedance, RIN as follows:
With the transformer voltage of 0.3 VPP, each input (VIN+ and VIN-) swings from 105.3 mV to 171.0 mV or about 65.7 mVPP. The input voltages are shown in Figure 27.
Differential Input Analysis Assume that the LMH6555 is used as a differential amplifier with a transformer with its Center Tap at ground as shown in Figure 26:
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Assuming transformer secondary, VIN, of 300 mVPP
FIGURE 27. Input Voltages for Figure 26 Schematic Knowing the device input terminal voltages, one can estimate the differential input impedance as follows:
FIGURE 26. Differential Input Drive The input voltages (VIN+ and VIN-) can be derived using the technique explained previously. Assuming no transformer output and referring to the schematic of Figure 23:
This is comparable to RIN_DIFF found in the Electrical Characteristic table. OUTPUT STAGE AND GAIN ANALYSIS Differential gain is determined by the differential current flow through the feedback resistors RF1 and RF2 as shown in Figure 2. Current through RF1 (or RF2) sets the VOUT- (or VOUT+) swing. The nominal value of these resistors is close to 430. The LMH6555 output stage consists of two bipolar common emitter amplifiers with built in output resistances, RT1 and RT2, of 50, as shown in Figure 28.
The peak VIN+ and VIN- voltages can be determined using the transformer output voltage. Assuming there is 0.3 VPP of signal across the transformer secondary, 1/2 of that, or 0.15 VPP (75 mV peak), would appear at each input side (V1 or V2 in Figure 26). Here is the derivation of the LMH6555 input terminal's peak voltages.
When V1 swings positive, V2 will go negative by the same value, and vice versa. Therefore, the values derived above for Vx can be used to determine the average emitter voltage, as described earlier:
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FIGURE 28. Output Stage Including External Load RL
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LMH6555
With an output differential load, RL, of 100, half the differential swing between the output emitters appears at the LMH6555 output terminals as VOUT. With good matching between the input source impedances, RS1 and RS2 shown in Figure 24 and Figure 26, it is possible to infer the gain and output swing by inspection. The differential input impedance of the LMH6555, RIN_DIFF, is close to 78. In differential input drive applications, there is a balanced swing across the input terminals of the LMH6555, VIN+ and VIN-. So, by using the RIN_DIFF value, one determines the differential current flow through the input terminals and from that the output swing and gain.
The following is the expression for the Insertion Gain, AV_DIFF:
The expressions above apply equally to the single ended input drive case as well, as long as RS1 = RS2 = 50. For the case of the single ended input drive:
(4) For the special case where RS1 = RS2 = RS = 50 we have: This is comparable to AV_DIFF found in the Electrical Characteristic table.
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LMH6555
Physical Dimensions inches (millimeters) unless otherwise noted
16-Pin LLP NS Package Number SQA16A
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LMH6555 Low Distortion 1.2 GHz Differential Driver
Notes
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